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!"ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½_^ï¿½ï¿½ï¿½0/ DMEMCMBM^ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½DC%&' !"ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½_^ï¿½ï¿½ï¿½0/ DMEMCMBMï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ HIJKLMï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½3ï¿½3ï¿½3ï¿½3ï¿½3ï¿½3ï¿½4ï¿½4ï¿½4ï¿½4ï¿½4ï¿½46 6 666 6 HIJKLMï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ H I J K L M ï¿½ï¿½@ï¿½Hï¿½Dï¿½<ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½,ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½@ï¿½Dï¿½Hï¿½Lï¿½Pï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ ï¿½$ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½Xï¿½\ï¿½`ï¿½dï¿½hï¿½lï¿½pï¿½tï¿½0ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½ï¿½reg read -> block_id = 0x%X, operation = 0x%X, address = 0x%X, value = 0x%X, asd_ret = 0x%Xreg write -> block_id = 0x%X, operation = 0x%X, address = 0x%X, value = 0x%X, asd_ret = 0x%Xreg read 64b -> block_id = 0x%X, operation = 0x%X, address = 0x%llX, value = 0x%X, asd_ret = 0x%Xreg write 64b -> block_id = 0x%X, operation = 0x%X, address = 0x%llX, value = 0x%X, asd_ret = 0x%Xreg read -> operation = 0x%X, address = 0x%X, value = 0x%X, sys_drv_ret = 0x%Xreg write -> operation = 0x%X, address = 0x%X, value = 0x%X, sys_drv_ret = 0x%Xreg read 64b -> operation = 0x%X, address = 0x%X, value = 0x%llX, sys_drv_ret = 0x%Xreg write 64b -> operation = 0x%X, address = 0x%X, value = 0x%llX, sys_drv_ret = 0x%Xpcs_ras_inject_dataloss_error_mi100pcs_ras_inject_reply_buf_underflow_error_mi100pcs_ras_inject_elastic_buf_overflow_error_mi100pcs_ras_inject_reply_buf_overflow_error_mi100Sucessfully programmed SDMA 4.4 error injection on instance (%d) subblock (%d)UTCL2_ROUTER_GROUP10_VML2_REQ_FIFO10UTC_VML2_IFIFO_GROUP10GFX_TCX_GROUP10UTCL2_ROUTER_GROUP20_VML2_REQ_FIFO20UTC_VML2_IFIFO_GROUP20UTC_VML2_CACHE_PDE0_MEM0UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM0UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM0UTC_VML2_CACHE_PDE1_MEM0UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM0UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM0UTC_VML2_CACHE_PDE2_MEM0UTC_VML2_BANK_CACHE_0_4K_MEM0UTC_VML2_BANK_CACHE_1_4K_MEM0UTC_VML2_BANK_CACHE_2_4K_MEM0UTC_VML2_BANK_CACHE_3_4K_MEM0UTC_VML2_BANK_CACHE_0_BIGK_MEM0UTC_VML2_BANK_CACHE_1_BIGK_MEM0UTC_VML2_BANK_CACHE_2_BIGK_MEM0UTC_VML2_BANK_CACHE_3_BIGK_MEM0GFX_TCP_UTCL1_LFIFO0UTCL2_ROUTER_GROUP0_VML2_REQ_FIFO0UTC_VML2_IFIFO_GROUP0GFX_TCX_GROUP0GFX_TCC_CACHE_DATA_BANK_0_0GFX_TCC_CACHE_DATA_BANK_1_0GFX_TCC_CACHE_DIRTY_BANK_0UTCL2_ROUTER_GROUP11_VML2_REQ_FIFO11UTC_VML2_IFIFO_GROUP11GFX_TCX_GROUP11UTCL2_ROUTER_GROUP21_VML2_REQ_FIFO21UTC_VML2_IFIFO_GROUP21GFX_CPC_ME1_DC_CSINVOC1UTC_VML2_CACHE_PDE0_MEM1UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM1UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM1UTC_VML2_CACHE_PDE1_MEM1UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM1UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM1UTC_VML2_CACHE_PDE2_MEM1UTC_VML2_BANK_CACHE_0_4K_MEM1UTC_VML2_BANK_CACHE_1_4K_MEM1UTC_VML2_BANK_CACHE_2_4K_MEM1UTC_VML2_BANK_CACHE_3_4K_MEM1UTC_VML2_BANK_CACHE_0_BIGK_MEM1UTC_VML2_BANK_CACHE_1_BIGK_MEM1UTC_VML2_BANK_CACHE_2_BIGK_MEM1UTC_VML2_BANK_CACHE_3_BIGK_MEM1GFX_TCP_UTCL1_LFIFO1UTCL2_ROUTER_GROUP1_VML2_REQ_FIFO1UTC_VML2_IFIFO_GROUP1GFX_TCX_GROUP1GFX_TCC_CACHE_DATA_BANK_0_1GFX_TCC_CACHE_DATA_BANK_1_1GFX_TCC_CACHE_DIRTY_BANK_1UTCL2_ROUTER_GROUP12_VML2_REQ_FIFO12UTC_VML2_IFIFO_GROUP12GFX_TCX_GROUP12UTCL2_ROUTER_GROUP22_VML2_REQ_FIFO22UTC_VML2_IFIFO_GROUP22UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM2UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM2UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM2UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM2UTCL2_ROUTER_GROUP2_VML2_REQ_FIFO2UTC_VML2_IFIFO_GROUP2GFX_TCX_GROUP2GFX_TCC_CACHE_DATA_BANK_0_2GFX_TCC_CACHE_DATA_BANK_1_2UTCL2_ROUTER_GROUP13_VML2_REQ_FIFO13UTC_VML2_IFIFO_GROUP13GFX_TCX_GROUP13UTCL2_ROUTER_GROUP23_VML2_REQ_FIFO23UTC_VML2_IFIFO_GROUP23UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM3UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM3UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM3UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM3UTCL2_ROUTER_GROUP3_VML2_REQ_FIFO3UTC_VML2_IFIFO_GROUP3GFX_TCX_GROUP3GFX_TCC_CACHE_DATA_BANK_0_3GFX_TCC_CACHE_DATA_BANK_1_3UTCL2_ROUTER_GROUP14_VML2_REQ_FIFO14UTC_VML2_IFIFO_GROUP14GFX_TCX_GROUP14UTCL2_ROUTER_GROUP24_VML2_REQ_FIFO24UTC_VML2_IFIFO_GROUP24UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM4UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM4UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM4UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM4UTCL2_ROUTER_GROUP4_VML2_REQ_FIFO4UTC_VML2_IFIFO_GROUP4GFX_TCX_GROUP4UTCL2_ROUTER_GROUP15_VML2_REQ_FIFO15UTC_VML2_IFIFO_GROUP15UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM5UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM5UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM5UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM5UTCL2_ROUTER_GROUP5_VML2_REQ_FIFO5UTC_VML2_IFIFO_GROUP5GFX_TCX_GROUP5UTCL2_ROUTER_GROUP16_VML2_REQ_FIFO16UTC_VML2_IFIFO_GROUP16UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM6UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM6UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM6UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM6UTCL2_ROUTER_GROUP6_VML2_REQ_FIFO6UTC_VML2_IFIFO_GROUP6GFX_TCX_GROUP6UTCL2_ROUTER_GROUP17_VML2_REQ_FIFO17UTC_VML2_IFIFO_GROUP17UTC_ATCL2_CACHE_4K_BANK0_WAY0_MEM7UTC_ATCL2_CACHE_4K_BANK1_WAY0_MEM7UTC_ATCL2_CACHE_4K_BANK0_WAY1_MEM7UTC_ATCL2_CACHE_4K_BANK1_WAY1_MEM7UTCL2_ROUTER_GROUP7_VML2_REQ_FIFO7UTC_VML2_IFIFO_GROUP7GFX_TCX_GROUP7UTCL2_ROUTER_GROUP18_VML2_REQ_FIFO18UTC_VML2_IFIFO_GROUP18UTCL2_ROUTER_GROUP8_VML2_REQ_FIFO8UTC_VML2_IFIFO_GROUP8GFX_TCX_GROUP8UTCL2_ROUTER_GROUP19_VML2_REQ_FIFO19UTC_VML2_IFIFO_GROUP19UTCL2_ROUTER_GROUP9_VML2_REQ_FIFO9UTC_VML2_IFIFO_GROUP9GFX_TCX_GROUP9GFX_TCC_RETURN_DATAGFX_TCC_IN_USE_DECGFX_CPC_ME1_DC_CSINVOCGFX_CPC_ME2_DC_CSINVOCGFX_TCC_WRITE_CACHE_READGFX_SQ_LDS_DGFX_CPC_UCODEUTC_VML2_BANK_CACHEGFX_CPC_ME1_DC_RESTOREGFX_CPC_ME2_DC_RESTOREGFX_CPC_ME1_DC_STATEGFX_CPC_ME2_DC_STATEGFX_GDS_INPUT_QUEUEGFX_SQC_DATA_CU0_WRITE_DATA_BUFGFX_SQC_DATA_CU1_WRITE_DATA_BUFGFX_SQC_DATA_CU2_WRITE_DATA_BUFGFX_SQC_DATA_CU3_WRITE_DATA_BUFGFX_TCC_HIGH_RATE_TAGGFX_TCC_LOW_RATE_TAGGFX_CPF_TCIU_TAGGFX_CPC_SCRATCHGFX_TA_FS_AFIFO_HIGFX_TD_SS_FIFO_HIGFX_SQ_LDS_IUTC_ATCL2_CACHE_4K_BANKUTC_ATCL2_CACHE_2M_BANKGFX_TCC_RETURN_CONTROLGFX_RLC_SRM_DATA_RAMGFX_TCP_DB_RAMGFX_TCP_CACHE_RAMGFX_TCI_WRITE_RAMGFX_RLC_TCTAG_RAMGFX_SQC_BANKA_DATA_TAG_RAMGFX_SQC_BANKB_DATA_TAG_RAMGFX_SQC_BANKA_INST_TAG_RAMGFX_SQC_BANKB_INST_TAG_RAMGFX_RLC_SPM_SE0_SCRATCH_RAMGFX_RLC_SPM_SE1_SCRATCH_RAMGFX_RLC_SPM_SE2_SCRATCH_RAMGFX_RLC_SPM_SE3_SCRATCH_RAMGFX_RLC_SPM_SE4_SCRATCH_RAMGFX_RLC_SPM_SE5_SCRATCH_RAMGFX_RLC_SPM_SE6_SCRATCH_RAMGFX_RLC_SPM_SE7_SCRATCH_RAMGFX_RLCG_SCRATCH_RAMGFX_RLC_SPM_SCRATCH_RAMGFX_RLCV_SCRATCH_RAMGFX_SQC_BANKA_DATA_BANK_RAMGFX_SQC_BANKB_DATA_BANK_RAMGFX_SQC_BANKA_INST_BANK_RAMGFX_SQC_BANKB_INST_BANK_RAMGFX_TCP_LFIFO_RAMGFX_RLC_SRM_ADDR_RAMGFX_RLCG_INSTR_RAMGFX_RLCV_INSTR_RAMGFX_SQC_BANKA_DATA_DIRTY_BIT_RAMGFX_SQC_BANKB_DATA_DIRTY_BIT_RAMGFX_TCC_LATENCY_FIFO_NEXT_RAMGFX_EA_MAM_A0MEMGFX_EA_MAM_D0MEMGFX_EA_MAM_A1MEMGFX_EA_MAM_D1MEMGFX_EA_MAM_A2MEMGFX_EA_MAM_D2MEMGFX_EA_MAM_A3MEMGFX_EA_MAM_D3MEMGFX_EA_GMIWR_DATAMEMGFX_EA_DRAMWR_DATAMEMGFX_EA_IOWR_DATAMEMGFX_EA_GMIRD_CMDMEMGFX_EA_DRAMRD_CMDMEMGFX_EA_IORD_CMDMEMGFX_EA_GMIWR_CMDMEMGFX_EA_DRAMWR_CMDMEMGFX_EA_IOWR_CMDMEMGFX_EA_GMIRD_PAGEMEMGFX_EA_DRAMRD_PAGEMEMGFX_EA_GMIWR_PAGEMEMGFX_EA_DRAMWR_PAGEMEMGFX_EA_MAM_AFMEMGFX_EA_RRET_TAGMEMGFX_EA_WRET_TAGMEMGFX_SPI_WB_GRANT_30_MEMUTC_ATCL2_CACHE_2M_BANK0_WAY0_MEMUTC_ATCL2_CACHE_2M_BANK1_WAY0_MEMUTC_ATCL2_CACHE_2M_BANK0_WAY1_MEMUTC_ATCL2_CACHE_2M_BANK1_WAY1_MEMGFX_GDS_OA_PIPE_MEMGFX_GDS_OA_PHY_DATA_RAM_MEMGFX_GDS_OA_PHY_CMD_RAM_MEMGFX_SPI_GDS_EXPREQ_MEMGFX_SPI_SR_MEMGFX_GDS_MEMGFX_SPI_LIFE_CNT_MEMGFX_TCC_WRITE_RETURNGFX_TA_FS_CFIFOGFX_TA_FS_DFIFOGFX_SQC_DATA_CU0_UTCL1_LFIFOGFX_SQC_DATA_CU1_UTCL1_LFIFOGFX_SQC_DATA_CU2_UTCL1_LFIFOGFX_SQC_DATA_CU3_UTCL1_LFIFOGFX_SQC_INST_UTCL1_LFIFOGFX_TA_FL_LFIFOGFX_TA_FX_LFIFOGFX_TCC_UC_ATOMIC_FIFOGFX_TCC_SRC_FIFOGFX_TCP_CMD_FIFOGFX_TCC_CACHE_TAG_PROBE_FIFOGFX_TCA_HOLE_FIFOUTC_VML2_RDIF_LOG_FIFOGFX_TCP_VM_FIFOGFX_TCA_REQ_FIFOGFX_TD_CS_FIFOGFX_SQC_BANKA_INST_UTCL1_MISS_FIFOGFX_SQC_BANKB_INST_UTCL1_MISS_FIFOGFX_SQC_BANKA_DATA_MISS_FIFOGFX_SQC_BANKB_DATA_MISS_FIFOGFX_SQC_BANKA_INST_MISS_FIFOGFX_SQC_BANKB_INST_MISS_FIFOGFX_SQC_BANKA_DATA_HIT_FIFOGFX_SQC_BANKB_DATA_HIT_FIFOGFX_TCC_LATENCY_FIFOGFX_TA_FS_AFIFO_LOGFX_TD_SS_FIFO_LOUTC_VML2_QUEUE_REQGFX_CPF_ME1_ROQGFX_CPF_ME2_ROQGFX_TCC_IN_USE_TRANSFERUTC_VML2_WALKERUTCL2_ROUTERGFX_SQ_SGPRGFX_SQ_VGPRGFX_TCC_OUTPUT_FIFOSUTC_VML2_RDIF_ARADDRSUTC_VML2_QUEUE_RETInvoked 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